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Description
This book provides an overview of current Intellectual Property (IP) based System-on-Chip (SoC) design methodology and highlights how security of IP can be compromised at various stages in the overall SoC design-fabrication-deployment cycle. Readers will gain a comprehensive understanding of the security vulnerabilities of different types of IPs. This book would enable readers to overcome these vulnerabilities through an efficient combination of proactive countermeasures and design-for-security solutions, as well as a wide variety of IP security and trust assessment and validation techniques. This book serves as a single-source of reference for system designers and practitioners for designing secure, reliable and trustworthy SoCs.
Content:-
Part I: Introduction
1. Security and Trust Vulnerabilities in Third-Party IPs
Part II: Trust Analysis
2. Security Rule Check
3. Digital Circuit Vulnerabilities to Hardware Trojans
4. Code Coverage Analysis for IP Trust Verification
5. Analyzing Circuit Layout to Probing Attack
6. Testing of Side-Channel Leakage of Cryptographic Intellectual Properties: Metrics and Evaluations
Part III: Effective Countermeasures
7. Hardware Hardening Approaches Using Camouflaging, Encryption, and Obfuscation.
8. A Novel Mutating Runtime Architecture for Embedding Multiple Countermeasures Against Side-Channel Attacks
Part IV: Security and Trust Validation
9. Validation of IP Security and Trust
10. IP Trust Validation Using Proof-Carrying Hardware
11. Hardware Trust Verification
12. Verification and Trust for Unspecified IP Functionality
13. Verifying Security Properties in Modern SoCs Using Instruction-Level Abstractions
14. Test Generation for Detection of Malicious Parametric Variations
Part V: Conclusion
15. The Future of Trustworthy SoC Design
Index
1. Security and Trust Vulnerabilities in Third-Party IPs
Part II: Trust Analysis
2. Security Rule Check
3. Digital Circuit Vulnerabilities to Hardware Trojans
4. Code Coverage Analysis for IP Trust Verification
5. Analyzing Circuit Layout to Probing Attack
6. Testing of Side-Channel Leakage of Cryptographic Intellectual Properties: Metrics and Evaluations
Part III: Effective Countermeasures
7. Hardware Hardening Approaches Using Camouflaging, Encryption, and Obfuscation.
8. A Novel Mutating Runtime Architecture for Embedding Multiple Countermeasures Against Side-Channel Attacks
Part IV: Security and Trust Validation
9. Validation of IP Security and Trust
10. IP Trust Validation Using Proof-Carrying Hardware
11. Hardware Trust Verification
12. Verification and Trust for Unspecified IP Functionality
13. Verifying Security Properties in Modern SoCs Using Instruction-Level Abstractions
14. Test Generation for Detection of Malicious Parametric Variations
Part V: Conclusion
15. The Future of Trustworthy SoC Design
Index
Author Details
"PrabhatMishra"
"Swarup Bhunia"
"Mark Tehranipoor"
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